#news

Santa Clara's company officially presented its first general purpose discrete GPU, a component based on a new architecture and specifically designed for high performance computing applications. Future gaming chips will also be released.

Intel has long been working on its discrete GPU, a component capable of competing with NVIDIA and AMD in every market and for every type of application. The first battleground officially chosen by Santa Clara's company is High-Performance Computing (HPC), supercomputers and calculations dedicated to artificial intelligence. Intel has unveiled Ponte Vecchio, the first discrete GPU of the "exascale class" and specifically dedicated to HPC applications. Produced on an innovative 7-nanometer technological node, Ponte Vecchio will use the technology of 3D chips known as Foveros and will include everything needed to accelerate high-performance calculations.

Ponte Vecchio will mark the debut of Xe, a GPU architecture capable of translating into different declinations (thanks to Foveros and high-speed interconnections between the various chiplets) that can be proposed to customers in the HPC, cloud, multimedia transcoding, workstating and PC gaming environments and mobile / ultramobile systems.

 

 

Ponte Vecchio and Xe can then take advantage of oneAPI, yet another novelty announced by Intel regarding a development toolkit designed to unify the creation of optimized code to run on CPUs, GPUs, FPGAs and other "specialized accelerators" produced by Santa Clara's company. The actual arrival of Ponte Vecchio and the new Xe architecture on the market will coincide with the commissioning of Aurora, the HPC super-system on which Intel works on behalf of the US Department of Energy: the new US supercomputer will arrive in 2021, will incorporate several nodes (each based on six Ponte Vecchio GPUs plus two Xeon CPUs based on the future Sapphire Rapids architecture) and should represent the first computing unit in the world capable of breaking through the wall of 1 exaflops of computing capacity.